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Improving the Performance of WCET Analysis in the Presence of Variable Latencies

Abstract : Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time () analysis methods tend to scale poorly to modern hardware architectures. As a result, a tradeo must be made between the duration and the precision of the analysis, leading to an overestimation of the bounds. This in turn reduces the schedulability and resource usage of the system. In this paper we present a new data structure to speed up the analysis: the eXecution Decision Diagram (), which is an ad-hoc extension of Binary Decision Diagrams tailored for analysis problems. We show how s can be used to represent efficiently execution states and durations of instruction sequences on a modern hardware platform. We demonstrate on realistic applications how the use of an substantially increases the scalability of analysis.
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Contributor : Christine Rochange <>
Submitted on : Thursday, June 4, 2020 - 3:34:27 PM
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Zhenyu Bai, Hugues Cassé, Marianne de Michiel, Thomas Carle, Christine Rochange. Improving the Performance of WCET Analysis in the Presence of Variable Latencies. 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Jun 2020, London, United Kingdom. pp.119-130, ⟨10.1145/3372799.3394371⟩. ⟨hal-02777132⟩



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